The invention relates to an analog-to-digital converter integrated circuit which requires only a single data terminal and a single control terminal to provide communication with a controller to enable the controller to read a digital word representing an analog signal input to the analog-to-digital converter. The invention also relates to an embodiment of the analog-to-digital converter which is programmable via the data terminal.
Many systems require frequent conversion of analog signals into digital signals to be operated upon by a digital system, such as a microcontroller system or a digital signal processor (DSP) system. Consequently, there is a need for an inexpensive integrated circuit analog-to-digital converter (ADC) which can be conveniently and inexpensively coupled between the source of the analog signal (which typically might be an analog voltage or current signal) and the digital system. For a delta sigma ADC that receives an analog signal as a differential signal and utilizes an external reference voltage and an external system clock signal, at least six leads are required in addition to the leads required for communicating with the digital system. The six additional leads referred to include two leads for receiving the differential analog input signal, one lead for receiving the system clock signal, one lead for the supply voltage, one lead for the ground voltage, and one lead for the external reference voltage. If the analog-to-digital converter is to be packaged in a standard, economical 8-lead package, only two leads are available for connecting the ADC to the digital system.
Conventionally, delta sigma analog-to-digital converters are interfaced with microcontrollers using either a four-wire interface circuit, such as a standard SPI interface using a SCLK clock signal terminal, a data input terminal, a data output terminal, and a chip select terminal, or a similar three-wire interface circuit that eliminates the chip select terminal. In addition, a data valid terminal often is required.
One prior approach to making more leads available for communication between the ADC and the digital system is to provide the analog input signal as a single-ended signal rather than a differential signal. However, this results in analog-to-digital conversion inaccuracies caused by differences between the external ground voltage and the internal ground voltages.
Other prior techniques for making more leads available for communication between the ADC and the digital system has been to provide a precision internal voltage reference circuit and/or an internal clock signal source in the ADC integrated circuit chip. However, this greatly increases the chip size, which increases the chip cost and may prevent the use of presently available standard 8-lead packages such as an SOIC package.
So-called two-wire I2C interface systems can accomplish digital communication between a xe2x80x9cslavexe2x80x9d component and a xe2x80x9cmasterxe2x80x9d component using only two leads. However, each slave component must be addressable in the sense that it must store a unique address so it can respond to the unique address when the master presents it on the I2C bus. This requires providing circuitry for individually setting up the addresses in each slave device, either by providing additional leads or by using non-volatile memory elements. Both of these approaches to dealing with the addresses required in an I2C system are expensive and are inconsistent with the objective of providing an analog-to-digital converter which receives a differential input, external system clock, and external reference voltage in an 8-lead package.
Thus, there is a need for a non-addressable inexpensive analog-to-digital converter integrated circuit receiving a differential analog input signal, and utilizing an external reference voltage and an external clock signal, which is capable of operatively communicating with a digital system utilizing only two leads.
Accordingly, it is an object of the invention to provide a non-addressable integrated circuit delta sigma analog-to-digital converter which receives an analog input signal, an external reference voltage, and an external clock signal, and is capable of communication with a digital system by means of only two conductors.
It is another object of the invention to provide a flexible, low power, non-addressable integrated circuit delta sigma analog-to-digital converter which receives a differential analog input signal, an external reference voltage, and an external clock signal, and is capable of communication with a digital system by means of only two conductors.
It is another object of the invention to provide a non-addressable integrated circuit delta sigma analog-to-digital converter which receives a differential analog input signal, an external reference voltage, and an external clock signal, and is capable of communication with a digital system by means of only two conductors and is small enough in size to be packaged in a standard eight lead SOIC package.
It is another object of the invention to provide an integrated circuit delta sigma analog-to-digital converter which receives a differential analog input signal, an external reference voltage, and an external clock signal, is capable of communication with a digital system by means of only two conductors, and is programmable by the digital system.
It is another object of the invention to provide a two-wire interface by means of which a digital system can accomplish all needed communication with a digital port of another system.
Briefly described, and in accordance with one embodiment thereof, the invention includes a delta sigma modulator (103) adapted to produce a stream of pulses (104) the density of which represents the amplitude of an analog input signal (VIN) coupled to an input of the delta sigma modulator, a decimation filter (105) coupled to filter the stream of pulses and produce a digital word (106) representing the amplitude of the analog input signal, a serial interface circuit (109) coupled to receive the bits of the output word and serially shift the bits of the digital word to a data terminal (110), and a timing generator (17) operative in response to a clock signal (CLK) to produce timing signals to control operation of the delta sigma modulator 20 and the decimation filter. The timing generator also produces a conversion done signal (21) indicative of completion of conversion of the analog input signal (VIN) into the digital word. A control circuit (107) operates in response to the conversion done signal to produce a data ready signal (32) on the data terminal (110) and also operative in response to a digital control signal (SCLK) to cause the serial interface circuit to serially shift the bits of the digital word onto the data terminal.
In the described embodiments, the serial interface circuit (109) includes a shift register (20) having a shift clock input terminal coupled to the control circuit (107), a data input terminal(s) coupled to an output of the decimation filter (105) to receive the data word (106) and an output terminal coupled to the data terminal (110). The timing generator (17) produces the timing signals to control operation of the delta sigma modulator and the decimation filter so as to automatically and repeatedly effectuate a complete conversion of the analog input signal to the digital word and then generate the conversion done signal (21). The timing generator (17) supplies an internal clock signal (53) to the controller circuit (107) in response to the clock signal (CLK). The timing generator (17) also resets an internal timing signal (52) to reset the decimation filter in response to a reset signal (37) produced by the control circuit (107). The control circuit (107) produces a number of shift pulses (18) on the shift clock input terminal equal to the number of bits of the digital word in response to an equal number of pulses of the digital control signal (SCLK). The control circuit (107) operates to detect a first condition wherein the digital control signal (SCLK) is at a first level for a first interval that is at least as long as the duration required to complete a first number of conversion cycles and produces the reset signal (37) on a reset input terminal of the timing generator (17) in response to the detecting. The timing generator (17) performs the functions of resetting the timing sequences of the delta sigma modulator (103) and decimater (105) in response to the reset signal (37). This causes a plurality of the analog-to-digital converters (100), each having its timing generator (17) coupled to the same digital control signal, (SCLK) become internally synchronized when the digital control signal returns from the first level to a second level. The control circuit (107) operates to detect a second condition wherein the digital control signal (SCLK) is at the first level for a second interval that is substantially longer than the first interval and, in response to the detecting, produces a power down signal (38) on a power down input terminal of the delta sigma modulator and also on a power down input terminal of the decimation filter. There is a maximum number of intervals of the clock signal (CLK) that occur from the time of occurrence of the data ready signal (32) during which the current data representing the digital word can be shifted onto the data terminal. A timer (16) in the control circuit (107) counts that number of pulses of the clock signal (CLK) and then reestablishes the condition (40) necessary to start a new analog-to-digital data conversion cycle.
In one embodiment, the serial interface circuit (109) includes a bi-directional interface circuit (24) having a first terminal coupled to the data terminal (110A) and a second terminal coupled to the output terminal (110) of the shift register (20), and the control circuit (107) includes a command register (25) having an input-output port coupled to an input-output port (27) of the bi-directional interface circuit (24) to allow the command register (25) to receive data from the data terminal (110A) via the bi-directional interface circuit (24) and vice versa. The control circuit also includes a state machine circuit (26) operative to decode data in the command register (25) to produce a plurality of programmable control signals. The amplifier is a programmable gain amplifier and one of the programmable control signals is a gain control signal applied to a gain control input of the programmable gain amplifier. Another programmable control signal is applied to the decimation filter to control its decimation ratio. Another programmable control signal is applied to the bi-directional interface circuit to control the direction of information flow on the data terminal (110A).